Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge and is separated from source and drain regions contained in a substrate by a layer of thin oxide. Each of the memory cells can be electrically charged by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the substrate through the oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
FIG. 1 illustrates a typical floating-gate flash memory cell 1. The memory cell 1 comprises a floating gate 4 that is isolated between a tunnel oxide 2 and an interpoly dielectric 6, and a control gate 8. The floating-gate 4 is typically doped polysilicon. The tunnel oxide 2 typically has a thickness of from 80 Å to 100 Å so that erasing can be performed through channel by Fowler-Nordheim (FN) tunneling while good charge retention is still maintained. The coupling ratio between the floating gate 4 and the control gate 8 needs to be great enough, for example, at about 0.8. Sufficient coupling area is needed between the floating gate 4 and the control gate 8. Oxide-nitride-oxide (ONO) dielectric with a thickness of between about 150 Å and about 300 Å is typically used as the interpoly dielectric 6 between the floating gate 4 and control gate 8 since it combines the high k value of the silicon nitride and good characteristics of the silicon dioxide.
The flash memory cell 1 is typically programmed by channel hot electrons, which are generated by channel current and injected into the floating gate 4. With drain 12 and control gate 8 biased at around 5V to 8V, the programming time is typically in micro-second range. The flash memory cell 1 has a threshold voltage Vt that increases with the charge stored at the floating gate 4. The electrons stored in the floating gate also affect the channel current. Therefore, the magnitude of Vt or channel current can be used to determine values stored in the memory cell. Stored electrons are typically removed by FN tunneling through the channel to the substrate with a high negative voltage, for example, −10V, applied to the control gate 8.
Hot electrons can also be generated from avalanche breakdown at the drain junction and thus cause impact ionization. However, in conventional memories employing an avalanche breakdown mechanism, the breakdown region is well below the channel surface. The injection efficiency is typically lower than about 0.01%. Furthermore, if a laterally diffused drain is used in a memory cell, the drain junction breakdown can only occur at a much higher bias. Thus, there is a need for improving injection efficiency and lowering bias voltages. It is also highly preferred that operation voltages are not higher than the core operation voltage of the integrated circuit.
An i-MOS device, where “i” stands for intrinsic, is also known in the art. A typical i-MOS device is illustrated in FIG. 2. The i-MOS device has a heavily doped p-type region 30 and an n-type region 32 separated by an intrinsic region 33. A gate 38 is above the intrinsic region 33 to control the channel. The i-MOS device has an offset channel region 34 between the source 30 and gate-edge 35. When the channel 36 underneath the gate is inverted by the gate bias, the drain-source voltage drops mainly across the offset region 34 and triggers avalanche breakdown.